Assignment of the feedback interface

時(shí)間：2021-07-28作者：上海騰希電氣技術(shù)有限公司瀏覽：92

Assignment of the feedback interface



Feedback interface

The user program receives current values and status information from the X142 interface technology I/Os over the feedback interface.

The following table shows the feedback interface assignment:

列表: Assignment of the feedback interface

Offset from start address	Parameter		Meaning
Byte 0	STS_DI (DI0 to DI7)		State DI (DI0 to DI7)
Byte 1 to 3	Reserved		Must not be used
Byte 4 to 7	TEC_IN (DI0)		Timer DI: Byte 0, 1: 2nd TIME/OFF TIME (second input time stamp) Byte 2, 3: 1st TIME/ON TIME (first input time stamp)
			Oversampling DI: Byte 0 to 3: Oversampling value
			Event/period duration measurement	Event measurement: Byte 0, 1: Reserved Byte 2, 3: Counter value
Byte 8 to 11	TEC_IN_EXT (DI0)			Time period measurement: Byte 0 to 3: Measured time period
Byte 12 to 15	TEC_IN (DI1)		See byte 4 to 11
Byte 16 to 19	TEC_IN_EXT (DI1)
Byte 20 to 23	TEC_IN (DI2)
Byte 24 to 27	TEC_IN_EXT (DI2)
Byte 28 to 31	TEC_IN (DI3)
Byte 32 to 35	TEC_IN_EXT (DI3)
Byte 36 to 39	TEC_IN (DI4)
Byte 40 to 43	TEC_IN_EXT (DI4)
Byte 44 to 47	TEC_IN (DI5)
Byte 48 to 51	TEC_IN_EXT (DI5)
Byte 52 to 55	TEC_IN (DI6)
Byte 56 to 59	TEC_IN_EXT (DI6)
Byte 60 to 63	TEC_IN (DI7)
Byte 64 to 67	TEC_IN_EXT (DI7)
Byte 68	LEC (DI0, DI1)		Bit 4 to 6: Lost Edge Counter for DI1 Bit 0 to 2: Lost Edge Counter for DI0 Bit 3, 7: Reserved (must not be used)
Byte 69	LEC (DI2, DI3)		Bit 4 to 6: Lost Edge Counter for DI3 Bit 0 to 2: Lost Edge Counter for DI2 Bit 3, 7: Reserved (must not be used)
Byte 70	LEC (DI4, DI5)		Bit 4 to 6: Lost Edge Counter for DI5 Bit 0 to 2: Lost Edge Counter for DI4 Bit 3, 7: Reserved (must not be used)
Byte 71	LEC (DI6, DI6)		Bit 4 to 6: Lost Edge Counter for DI7 Bit 0 to 2: Lost Edge Counter for DI6 Bit 3, 7: Reserved (must not be used)
Byte 72	Reserved		Must not be used
Byte 73	Layout property		Specific value
Byte 74, 75	ZSW	SSL	Bit 12 to 15: Sign of life counter (slave sign of life)
		---	Bit 10, 11: Reserved (must not be used)
		SYNC	Bit 8: X142 interface is synchronized with user program
		Channel address	Bit 4 to 7 and 9: Number of the respective DI or DQ
		Channel mode	Bit 0 to 3: Operating mode of the respective DI or DQ

Substitute value behavior

If the CPU is in STOP, the digital outputs (irrespective of any inversion set) return "0" (LOW level) as a substitute value.

Reading back the terminal state

STS_DI (offset byte 0 of the feedback interface) represents the logical channel status, taking account of any inversion configured.

Digital inputs

With digital inputs (DI, Timer DI, oversampling DI, event/period measurement), the value corresponds to the logical state of the digital input.

Digital outputs

With digital outputs (DQ, Timer DQ, oversampling DQ, pulse width modulation PWM), the value corresponds to the actual terminal state of the digital output. If the terminal state deviates from the controlled state, there may be an output driver short-circuit or defect.




提示 STS_DI Signals are only reliably acquired over STS_DI if the level is significantly longer than the input delay + acquisition cycle of the digital inputs/outputs (X142). Example: If you operate the digital inputs/outputs (X142) as isochronous to the MC Servo in a cycle of 2 ms and a set input delay of 125 μs, the level duration must be > 2.125 ms.


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